1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a dynamic random-access-memory (RAM) having a self-refreshing mode.
1. Description of the Related Art
One example of RAM device of this type has been illustrated in FIG. 5, which has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. Heisei 5-41085. In the example shown, switching elements (transfer gates) which can independently control electrical ON and OFF between respective node points of bit or bit line pairs and respective node points of internal node pair of the sense amplifier, are provided for reducing operation current.
In the circuit of FIG. 5, each memory cell element forming the memory cell array comprises one transistor and one capacitor. In the example shown, respective memory cell elements are formed with cell transistors 31 to 38 and cell capacitors 41 to 48 for storing information. FIG. 5 shows the memory cell array of 4 bits.times.2 word for the purpose of illustration and for simplification.
The cell capacitors (hereinafter referred to as "memory cell") 41 and 42 of the first bit perform reading out and writing in of information on respective bit lines 81 and 82 of a bit line pair. The memory cells 43 and 44 of the second bit perform reading out and writing in of information on respective bit lines 83 and 84 of the bit line pair. Similarly, the memory cells 45 and 46 of the third bit perform reading out and writing in of information on respective bit lines 85 and 85 of the bit line pair. Also, the memory cells 47 and 48 of the fourth bit perform reading out and writing in of information on respective bit lines 87 and 88 of the bit line pair.
The memory cell transistors 31, 33, 35 and 37 of the first word are controlled ON and OFF by a word line 94. On the other hand, the memory cell transistors 32, 34 36 and 38 of the second word are controlled ON and OFF by a word line 93.
Sense amplifiers 11 to 14 are provided corresponding to respective bit line pair for detecting and amplifying information of corresponding bit pairs.
Transfer gates 21 to 28 are provided for controlling ON and OFF between respective internal node points (input/output nodes) 71 to 78 of the sense amplifier and the bit lines 81 to 88. The transfer gates 21, 23, 25 and 27 are simultaneously switched ON and OFF by a gate control signal 92. On the other hand, the transfer gates 22, 24, 26 and 28 are simultaneously switched ON and OFF by a gate control signal 91.
Between bit lines forming respective bit line pairs, transistors 61 to 64 are provided for balancing respective bit lines at the equal potential. These transistors 61 to 64 are controlled to be switched 0N and OFF by a balance pre-charge control signal 95.
On the other hand, pre-charge transistors 51 to 58 are provided corresponding to respective bit line pairs. By turning ON these transistors 51 to 58 by the balance pre-charge control signal 95, corresponding bit lines are pre-charged at (1/2)Vcc via the transistors 51 to 58. The (1/2)Vcc is generated by a power source circuit 97.
A control circuit 100 generates the control signals 91 to 95.
The operation of the circuit shown in FIG. 5 is shown in detail with reference to the timing charts of FIG. 6(A)-(E). The discussion is given with respect to memory cells 43 and 45 respectively storing high level data and low level data.
At first, the word line 94 is selected. Then, the data stored in the memory cells 43 and 45 are read out to the bit lines 83 and 85 via the cell transistors 33 and 35. Then, the data read out to the bit lines 83 and 85 is transferred to the nodes of the sense amplifier 74 and 75 via the transfer gates 23 and 25.
Next, the difference potential of the [digit] bit lines is gradually amplified by the sense amplifiers 12 and 13. In conjunction therewith, the gate control signals 91 and 92 are set to a low level to shut off the transfer gates 23, 24, 25 and 26 and thus electrically shut off the bit lines. By this, the nodes at which potentials be amplified are limited to the sense amplifier. Therefore, it becomes unnecessary to charge and discharge the capacity of the bit line to make high speed sense operation and thus high speed access possible.
After the potentials at the nodes in the sense amplifier being sufficiently amplified, only transfer gate control signal 92 is set to a high level to connect the bit lines 83 and 85 connected to the memory cells 43 and 45, from which data is read out. Therefore, the memory cells 43 and 45 are connected to the nodes 73 and 75 of the sense amplifiers 12, 13 to perform rewriting of data to the memory cells 43 and 45. For efficiently writing the high level data in the word line 94, the transfer gate control signal 92 upon re-writing is boosted at the level higher than or equal to the power source voltage Vcc of the electric power source of the memory circuit.
Finally, upon resetting, the word line 94 is set at low level to shut off the cell transistors 33 and 35. The other gate control signal 91 is set at high level (timing t1) to connect the bit lines 84 and 85 to the nodes 74 and 76 in the sense amplifier. Also, by setting the balance pre-charge control signal 95 to high level (timing t2), the bit line pairs 83, 84 and 85, 86, and the (1/2)Vcc power source line 96 are mutually connected to establish a balance of the bit lines and to pre-charge at (1/2)Vcc level.
In the sequence of operation set forth above, after potentials of the bit lines 84, 86 are amplified at a slight level to the extent not to cause malfunction of the sense amplifier by the operation noise of the gate control signal, the bit lines 84 and 86 are not charged and discharged from the sense amplifier power source. Furthermore, the bit lines, in which cell data are amplified at high level and low level, exchanges charge via the (1/2)Vcc power source line 96, the charge is cancelled in calculation.
Namely, upon pre-charging (timing at t2 and subsequent timing), if number of cells charged at high level and number of cells charged at low level are equal to each other, the charges of the bit lines are canceled. Therefore, arithmetically, charging and discharging is not performed from the (1/2)Vcc power source line 96. All charge and discharge current of the bit line becomes 1/2 when both of bit lines of the bit line pair are to be amplified. Therefore, significant reduction of the operation current can be achieved.
The conventional semiconductor memory device may reduce the charge and discharge current of the bit lines to be half, in calculation. However, in practical operation, since charge and discharge current may flow upon balance pre-charging, the charge and discharge current cannot be reduced to [be] half. Namely, since the balance pre-charge control signal and so forth flows for a long distance through the memory cell array, the operational wave form may be rounded.
When the level of the control signal 95 exceeds the potential on the bit line 85 so as to be greater than or equal to a threshold voltage of an NMOS transistor, both of the transistors 55 and 63 becomes conductive to establish a balance between the bit lines 85 and 86 of the bit line pair. Then, the bit line 85 is connected to the (1/2)Vcc power source line 96. Subsequently, when the level of the signal exceeds the potential on the bit line 84 so as to correspond to the threshold voltage, both of the transistors 54 and 62 become conductive to establish balance between the [digit] bit lines 83 and 84 of the [digit] bit line pair. Then, the [digit] bit line 84 can be connected to the (1/2)Vcc power source line 96.
Though the process set forth above, the (1/2)Vcc power source line 96 is connected to bit lines 84, 85 having lower potential than (1/2)Vcc, namely to the bit lines at the lower level side in all bit line pairs irrespective of high level or low level of the data in the memory cells. Therefore, the (1/2)Vcc power source line 96 may lower the level due to discharge of the potential.
Accordingly, during the period set forth above, the [digit] bit line 84 and 85 and so forth are charged via the (1/2)Vcc power source line 96 from the power source of a power source circuit 97.
Finally, when the level of the balance precharge control signal 95 exceeds the potential of the (1/2)Vcc power source line so as to correspond to the threshold voltage, the transistors 53 and 56 become conductive to connect the bit lines 83 and 86 to the (1/2)Vcc power source line 96. By this, all of the transistors 53, 54, 55, 56, 62 and 63 for balance precharging are placed into the conductive state.
At this time, the charge supplied from the (1/2)Vcc power source circuit 97 generated in the former half process of balancing pre-charging, becomes extra, the grounding line of the power source circuit 97 is discharged through the (1/2)Vcc power source line 96.
Accordingly, upon balance pre-charging, due to difference of conduction timing of the pre-charge transistors caused by level difference between the bit lines, wasteful charging and discharging of current may be caused.